iRadio

FAQ about iRadio

Q: Why do you need a high-end real-time wireless prototype?

A: A high-end wireless prototype can be used a platform upon which new algorithms and schemes can be developed, evaluated and validated, a baseline upon which system level solutions and network-based applications can be implemented and integrated, and a benchmark upon which the ASIC chip can be built. Such a prototype is expected to be flexible and scalable to accommodate with a wide range of signal formats and support various activities related to research, education to product development. The success in prototyping of an advanced wireless communications system represents a noteworthy and meaningful progress in the development of a modern wireless communications system, which helps major grant application, validates interested algorithms and schemes, and lays down a truthful foundation for next step ASIC design.

Q: Why FPGA is most suitable solution to the prototype of an advanced wireless communications systems?

A: The common solutions to the baseband processing of an advanced wireless prototype are computer simulations, digital signal processor (DSP) and field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). The comparisons of the solutions are summarized in Table I.

Table I: Comparison of the solutions to the baseband processing of a wireless prototype

	Simulations	DSP	FGPA	ASIC
Functionality	X	X	X	X
Complexity	No considered	Related	Highly Related	Determined
Real-time	Offline	Real-time	Real-time	Real-time
Speed	Low	Medium	Fast	Fast
Operation	In sequence	In sequence	In parallel	In parallel
Applications	General	General	General	Specific

Theoretically, a signal processing can be performed through using a simulation tool, such as Matlab, operating on a computer. However, the CPU of a computer is not specifically designed to support real-time processing although it runs at the fastest clock than any other processors or digital circuits. To explain this, let us take a look at an example. Figure 1 illustrates the diagram of signal processing of a Wi-Fi receiver.

Fig. 1 The diagram of baseband signal processing of a Wi-Fi receiver

The ten modules shown in Fig. 1 need to work simultaneously and most of them, such as synchronization, channel estimator, FFT and Viterbi decoder models, need to perform a great number of multiplications and additions during a sampling clock period of 100ns. Unfortunately, CPU is designed to execute the instructions in sequence instead of in parallel which is highly required for hardware based wireless communications systems. The high date rates and MIMO option further exaggerate the difficulty. In addition, the overhead and non-constant latencies of operating system bring forward another critical issue for a CPU to perform a real-time baseband processing. Certainly, CPUs do not wait but aggressively push high its operation clock and multiple cores are now being integrated to realize parallel processing. However, until now upon the available commercialized computers, we conclude that CPU cannot afford the heavy computing required for a high-speed real-time communications system.

DSP is a special micro-processor running at a high clock and to be with several parallel functional units and hardware multipliers. FPGA looks like a huge warehouse storing up to millions of digital logic gates and hundreds of hardware multipliers that can be programmed for a specific signal processing function. ASIC is a competitive solution for commercialized communications systems but suffers from long development cycle, high investment risk and extremely expensive development cost, which is not suitable for prototyping stage. In addition, ASIC is not flexible at all. In fact, FPGA usually serves as the prototype for ASIC.

Now we narrow our choices between DSP and FPGA. In order to compare their performances, let us take an example of a 16-bit multiplier. The fastest DSP chip, based on our knowledge, is TMS320C6474 from TI. This chip has an operation capability expressed as 28,800 millions instructions per second (MIPS), which means 28,800 millions multiplications can be finished within 1s. This DSP chip sells for $170/unit. In a similar price, a FPGA chip of EP3C55 from Altera can be bought, which integrates 156 multipliers at a clock of 250MHz, and 55k logic elements (LEs) at a clock of 437.5MHz. Every 266 LEs in this FPGA chip can be synthesized as a multiplier. Therefore, the total number of multiplications that the FPGA chip can conduct within 1s is calculated by 156 × 250 + (55000/266) × 437.5 millions = 129,460 millions, which is about 3.5 times more than that of DSP. With a higher price, FPGA chips triple the number of LEs and double operation speed, but no faster DSP can be found at this moment. Except ASIC, FPGA is the fastest and cheapest solution for wireless communication systems. However, a drawback of FPGA lies on its longer synthesis time when compared to the compilation time needed for DSP. This problem is being largely alleviated by using advanced synthesis tools and faster computers with large memory sizes. Another drawback of FPGA is that the hardware description language programming is more complicated than C programming based on DSP.

Q: What distinguishes iRadio with other software defined radios (SDR) ?

A: SDR has been intensively practiced in the past decade but ending up with no commercial SDR mainly due to the expensive hardware, slow operation speed even through when the fastest DSP nowadays is applied, long development cycle and high requirement for the knowledge of developers ranging from signal processing, communications theory, DSP/FPGA hardware and algorithm programming. iRadio is fully implemented based on FPGA that can meet the strict requirement of heavy computing without sacrificing performances. iRaido adopts an embedded DSP core, Nois II, to realize MAC protocol simplifying the architecture. Meanwhile, iRdio adopts fast Ethernet interface to exchange data with host computers. iRaido integrates our many years experience of SDR development and implementation. In addition, iRadio costs 1/3-1/4 or less of other SDR solutions provided by both the companies and Universities.

Q: How iRadio outperforms other FPGA-based solutions on the market?

A: iRadio is a real-time full functional radio built upon software defined radio technology and readily realizes multiple-mode operation. There are several companies and Universities that offer FPGA-based solutions to high-speed MIMO wireless prototyping. These companies can be accessed to through Internet and are also listed in the official Xilinx and Altera websites. For example, the SDR boards from the Sundance company, the Lyrtech company and Rice University can be reached through the following links:

http://www.sundance.com/web/files/productpage.asp?Strfilter=SMT8096

http://www.lyrtech.com/Documents/product_sheets/Reference%20sheet%20-%20MIMO%20ADS%20%28hi_res%29.pdf

http://www.mangocomm.com/products/boards/warp-fpga-board-v2

Table II compares the performances among the UMD solution and Sundance, Lyrtech and Rice University.

	iRadio	Sundance	Lyrtech	Rice University
MIMO	8 × 8	1 × 1	4 × 4	4 × 4
FPGA (LEs)	Stratix III, 300K	Virtex 4, 35K	Virtex 4, 25-160K	Virtex-4, 100K
DSP	Nios II	C6416	C6416	PowerPC (2)
SDRAM	4GB	256MB	2GB	2GB
Bandwidth	Wideband	Wideband	13.5/40MHz	20MHz
Form factor	Standalone	PCI	cPCI	Standalone
Software	UMD	Third party, bad	Lyrtech	Rice University
Price (estimate)	$5,390	$8,000	High	>10K

Q: What feature with iRadio to 8 × 8 high-speed MIMO wireless prototype?

A: There are several challenges in the design of a real-time high-speed wireless prototype. At first, an 8 × 8 MIMO configuration requires 16 ADCs and 16 DACs. If the resolution of ADC/DAC is selected to be 14 bits, the number of IO interfaces to the FPAG is as many as 16 × 2 × 14 = 448, which generates a challenge for PCB design and data multiplexing. Fortunately, the Terasic company has done a good job to offer off-the-shelf FGPA boards that can support 8 × 8 MIMO configuration by integrating two of such boards directly.

The high-speed real-time data exchange mechanism between the prototype and the host computer becomes another challenge, which requires knowledgeable design and cooperation among hardware, firmware and software. Based on our experience, the efforts spent on building up the data path are comparable to that of developing baseband algorithms themselves, although the latter is what we want to focus on.

MAC protocols are expected to handle interrupts, iterations, loops, timers, and state transitions, which are more readily realized upon a processor instead of a FPGA. However, except increasing the cost and size, the integration of a separated processor raises a challenge related to high-speed data exchange between the processor and the FPGA.

In short, data transfer between two modules in a high-speed real-time system requires significant efforts and time consuming design. A good prototype should minimize extra efforts on data path and interfacing, which allows users to focus on the algorithm development for rapid prototyping. Unfortunately, in the past a few years we did not find such a solution including any one from the solutions listed above that is capable to do so. This motivates us to develop a ZERO EFFORT high-speed real-time wireless communications prototype for wireless communications systems researchers and designers.

The architecture of the UMD solution is shown in Fig. 2. Payload data are sent from and received by the host computer through an Ethernet interface. The Nios II processor embedded in FPGA listens to the socket, obtains payload data and applies MAC layer functions. MAC frames are then written to a first in first out (FIFO) data buffer which exchanges data between MAC layer and physical layer in a real-time mode. The data further pass through physical layer modules consisting of scrambler, encoder, interleaver, QAM modulation and FFT, one by one. (Again, here we use Wi-Fi signals as an example). Finally OFDM baseband signals are formed and converted to analog signals through two ADCs in a quadrature format. The receiver performs inverse processing and retrieves the payload data, which are ultimately sent back to the host computer through the Ethernet interface for high layer applications.

Fig. 2 The system architecture of an MIMO wireless prototype proposed by iRadio

The prototype features with the following aspects.

(1) This prototype has a simple and standalone architecture resulting in a portable solution when compared to other PCI or VEM based solutions.
(2) The large size of LEs of the FPGA adopted in the prototype supports for complicated algorithms that are critical for realizing 8 × 8 MIMO algorithms and future applications.
(3) A Nios II processor embedded in FPGA instead of a separated DSP reduces the complexity and cost of the prototype in a large degree.
(4) Gigabit Ethernet interface provisions for high-data exchange between prototype and host computer. High-speed data transfers between any two parts of the prototype will be demonstrated and related C/VHLD resource codes will be provided.
(5) A live video sharing program will be demonstrated to validate the system functions based on UDP/IP and ARQ protocols.
(6) A real-time testing tool will be offered to evaluate the performance including bit error rate (BER), frame error rate (FER) and frame latency.

Q: What are the main applications of iRadio?

A: The main applications of iRadio are for fast prototyping for advanced wireless communications and networks for research, engineering and education purposes. Examples are universal signal processing systems, fast real-time data acquisition systems and advanced wireless communications prototypes. Specifically, iRadio is caple to build up the prototype for ASIC design in WEEKS. Recently, we successfully built up 1) Smart Grid Radio based on the IEEE 802.15.4g standard (draft, OFDM based); 2) WAVE Prototype based on the IEEE 802.11p standard (draft); 3) WiMax Testbed and 4) LTE Advanced Radio for Internet Access for high-speed vehicles and trains.

Q: Does iRadio integrate any FPGA IP Cores ?

A: Fortunately, NO. We developed complete codes for MAC/Network protocols and baseband algorithms including time and frequency synchronizations, channel estimate, FFT, Viterbi/R-S Encoder, Modulations and multiple-stage Doppler/CFO estimator (refer to Patent #20090080576).

Q: What are your group offering now?

A: We are offering algorithms, modules, radios and solutions for the above advance wireless communications and networks. For more details and unanswered questions, please contact us.